Real-Time Hardware Implementation and Experimental Evaluation of a Modified dqPLL Architecture for Harmonic-Robust Three-Phase Grid Synchronization

This paper presents a real-time implementation and experimental evaluation of a modified synchronous reference frame phase-locked loop (dqPLL) for three-phase grid synchronization under harmonic distortion. The proposed architecture extends the conventional dqPLL with a dedicated harmonic compensation block designed to attenuate selected low-order harmonics while preserving the fundamental positive-sequence component required for accurate phase and frequency estimation. Real three-phase voltage signals acquired from the Spanish electricity grid using a Digilent Analog Discovery device were processed and implemented on a Real-Time Digital Simulator (RT Box 240) through AccurateRTDS software , enabling real-time experimental validation under realistic grid conditions. A quantitative comparison between the classical and modified dqPLL architec-tures was conducted in terms of frequency tracking, harmonic attenuation, total harmonic distortion (THD), transient behavior, and computational execution time. Experimental results show that the proposed dqPLL architecture limits frequency deviations to approximately ±0.2 Hz around the nominal 50 Hz, whereas the classical dqPLL exhibits oscillations of approximately ±8 Hz under harmonic 1 distortion. The results demonstrate that the proposed modification provides a practical compromise between harmonic rejection, synchronization accuracy, and computational complexity, making it suitable for real-time grid-connected power electronic applications. The proposed harmonic compensation mechanism attenuates the 5th, 7th, 11th, and 13th harmonic components by more than 90% and reduces the measured THD from 2.27% at the input to 1.101%. The modified dqPLL also provides improved frequency stability and reduced oscillatory behavior compared with the conventional architecture, at the expense of increased computational execution time.