Comparative analysis of a noise and count-rate performance of a charge-sensitive amplifier in planar CMOS and FinFET technologies for hybrid pixel detectors

This paper presents a comparative analysis of a charge-sensitive amplifier (CSA) for hybrid pixel detectors operating in a single-photon counting mode, implemented in a 40 nm planar complementary metal-oxide-semiconductor (CMOS) and a 16 nm fin field-effect transistor (FinFET) technologies. Hybrid pixel detectors are widely used in particle physics, synchrotron radiation facilities, and X-ray imaging applications, where front-end electronics must support increasingly high photon flux while maintaining low noise and a compact pixel area. A folded-cascode charge-sensitive amplifier was designed in both technologies and evaluated through circuit simulations in terms of open-loop gain, gain-bandwidth product, maximum counting rate, and equivalent noise charge (ENC). The 16 nm FinFET implementation achieved significantly higher intrinsic gain and gain-bandwidth product than the 40 nm planar CMOS design, resulting in a substantially higher maximum counting rate while maintaining comparable noise. These performance improvements, however, come at the cost of increased design complexity, reduced flexibility in transistor sizing, greater sensitivity to layout parasitics, and higher fabrication costs. The results demonstrate that FinFET technology offers strong potential for next-generation high-speed front-end readout electronics for hybrid pixel detectors, particularly in applications requiring high count-rate capability, while highlighting the design trade-offs associated with advanced technology nodes.