Key points are not available for this paper at this time.
The design of an asymmetric serial link poses a number of tradeoffs for the designer. This paper describes measurements from a 0.25 /spl mu/m CMOS test chip which show that a properly designed asymmetric link can achieve 2 Gb/s using single-ended signalling with a bit-error rate <10/sup -14/.
Chang et al. (Wed,) studied this question.