Ferroelectric Gate Stack Engineering with Tunnel Dielectric Insert for Achieving High MemoryWindow in FEFETs for NAND Applications

We experimentally demonstrate a novel gate stack engineering technique by introducing a Tunnel Dielectric Layer (TDL) between two Ferroelectric (FE) layers, significantly increasing the Memory Window (MW) in FEFETs. An 2 X improvement, from 2. 9 ~V in the reference device (without TDL) to 7. 5 ~V in the 8 / 3 / 8 configuration with TDL, was achieved within NAND thickness limit of 20 ~nm and write voltage 15 ~V. Impact of FE and TDL thickness in MW was also explored.