Design Framework for Ferroelectric Gate Stack Engineering of Vertical NAND Structures for Efficient TLC and QLC Operation

We report a framework for designing a ferroelectric gate stack for vertical NAND with efficient multi-bit performance by evaluating various gate stacks, including those with a tunnel dielectric layer (TDL), a gate blocking layer (GBL), different post-metallization annealing (PMA) temperatures and nanolaminates. Using the Memory Window (MW) slope as the primary design metric, our study reveals that the ferroelectric gate stack with both TDL and GBL has the potential to deliver the best multi-bit performance. Furthermore, adjusting the TDL/GBL thickness or PMA temperature can increase the minimum write voltage which can be helpful for reduced disturb. The results discussed herein provide design guidelines for optimizing ferroelectric gate stacks for improved multi-bit functionality and suitable switching voltages.