Heterojunction gate all around ferroelectric p-n-i-n tunnel FET with reduced Miller capacitance: a comprehensive analysis with analytical modeling and TCAD simulation

This research investigated the effects of ferroelectric layer thickness on the DC, analog/RF, and linearity performances of a heterojunction gate all around ferroelectric p-n-i-n tunnel field effect transistor (HJ-GAA-Fe-p-n-i-n TFET). An accurate analytical model for surface potential and drain current is developed for the proposed device, taking into account the source, channel, and drain depletion regions, the fringing field effect in the source and channel regions, and mobile charge carriers in the intrinsic channel region. A capacitance model has been developed utilizing the polarization effect produced by ferroelectric material in the gate stack, resulting in a significant reduction of parasitic Miller capacitance. A comprehensive study was conducted for the proposed device, taking into account non-idealities such as trap assisted tunneling, to obtain the DC characteristics, RF/analog parameters, and linearity performances, and comparing the results with and without the ferroelectric layer, as well as with a conventional TFET for low supply voltage operation. A step-by-step fabrication recipe for the proposed device is provided, which is compatible with the existing CMOS process flow. The model was assessed by TCAD simulation, producing notably consistent results. The reliability of the proposed HJ-GAA-Fe p-n-i-n TFET at lower supply voltage is highly promising for low-power analog and logic operations in the future semiconductor industry.