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This research aims to develop a mathematical model to determine drain current and short-channel effects in a specific type of transistor.

Computational Model for Drain Current and Short Channel Effects of Heterojunction GAA Nanowire TFET Featuring a Core‐Insulator

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This research aims to develop a mathematical model to determine drain current and short-channel effects in a specific type of transistor.
Formulated an analytical model using Kane's interband tunneling model and shortest tunneling length approach.
Performed numerical integration of tunneling generation rate over the entire device volume.
Evaluated the impact of various gate work functions, diameter of core-insulator, gate oxide thickness, and source doping concentration.
Drive current calculated at a 10 nm channel length under varying gate-source voltages (0.8 to 1 V).
Analytical model's results aligned with Silvaco 3D TCAD simulations, showing only a 7% marginal deviation.

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Randomized trial evaluates drain current in heterojunction GAA nanowire TFET, suggesting effective design improvements.

Singh et al. (2026) studied this question.

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