RISC-V Address-Encoded Byte Order Extension

In some cases, computer systems need to handle both little-endian and big-endian data, even if it differs from their native endianness. This paper proposes an RISC-V extension that makes it possible to remove the overhead introduced when dealing with foreign-endian data. It can be implemented with little engineering effort and a negligible impact on performance and hardware resources. Our results demonstrate that the extension can reduce the overhead of foreign-endian data processing by 62% or 37% compared to software-based solutions that use the base Instruction Set Architecture (ISA) or current bit manipulation extensions, respectively. This performance boost has the potential to benefit both new and legacy software once compiler and library support have been put in place.