The single inverter is affected by electromagnetic interference, and the protection mode

The easiest way to resist electromagnetic interference is to optimize the design to reduce interference. The electromagnetic interference received by a single inverter mainly comes from the influence of electromagnetic radiation on circuit topology and device type. Regarding circuit topology, it is recommended to adopt soft switching topologies such as active clamping flyback or LLC resonance, which can effectively reduce the voltage and current change rate in the switching process and reduce the switching noise by 6- 8 dB. In addition, multi-level technology can be introduced with 3-level or 5-level mating to control the output waveform THD to within 3%. In terms of changing the modulation strategy, such as using adaptive inverter PWM technology to adjust the switching frequency in real time to disperse harmonic energy, the switching loss can be reduced by about 30% with the dead time optimization algorithm. In terms of device selection, SiC MOSFETs with low gate charge (Qg<50nC) and low reverse recovery charge (Qrr<100nC) should be selected because their switching speed is more than 3 times faster than traditional silicon devices, which can significantly reduce high-frequency noise and thus reduce the impact. The PCB design must adopt a six-layer board stacking structure, including two complete power and ground planes. The key signal lines should be routed in strip wires, and the line widths should be accurately calculated according to the characteristic impedance requirements. In addition, the power loop layout should follow the principle of "shortest path", so that the area of the high-frequency current loop is less than 2cm², and low-inductance chip capacitors (such as 0402 package, capacitance 1nF) should be arranged between the drain-source of the MOSFET to absorb voltage spikes.