Investigation and fabrication of the 1200 V 4H-SiC trench MOSFET with double p-type shielding regions and multiple current spreading layers

In this paper, a silicon carbide (SiC) trench MOSFET with double p-type shielding regions and multiple current spreading layers (CSL) (DSMC-TMOS) is designed and fabricated experimentally. The P+ shielding region (P + SLD) at the trench bottom and the deep-implanted p-type shielding by both trench sides (DP) improve gate oxide robustness together. The P + SLD is grounded through layout design rather than a more complex process. One of the CSLs is introduced by epitaxy and another one is introduced by implantation. The impact of the P+SLD and CSLs on the characteristics of the DSMC-TMOS is studied by using numerical 2D simulation. Simulation results show that the P + SLD brings about a larger breakdown voltage (BV) and lower peak electric field in trench oxide ( E ox, peak ). However, the conduction characteristic is significantly degraded. Moreover, the multiple CSL layers can significantly reduce the specific on-resistance ( R on, sp ) while the blocking characteristic remains almost unchanged. The DSMC-TMOS has been manufactured and test results show that BV and R on of the DSMC-TMOS are 1460 V and 38.2 mΩ, respectively. Additionally, the impact of the key parameters is discussed, guiding subsequent optimization.