4H-SiC trench MOSFET with an integrated Schottky barrier diode and L-shaped P+ shielding region

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A novel 4H-SiC trench MOSFET is presented and investigated by simulation in this paper. The device features an integrated Schottky barrier diode and an L-shaped P+ shielding region beneath the gate trench and aside one wall of the gate trench (S-TMOS). The integrated Schottky barrier diode works as a free-wheeling diode in reverse recovery and reverse conduction, which significantly reduces reverse recovery charge (Q rr) and reverse turn-on voltage (V F). The L-shaped P+ region effectively shields the coupling of gate and drain, resulting in a lower gate–drain capacitance (C gd) and date–drain charge (Q gd). Compared with that of conventional SiC trench MOSFET (C-TMOS), the V F and Q rr of S-TMOS has reduced by 44% and 75%, respectively, with almost the same forward output current and reverse breakdown voltage. Moreover, the S-TMOS reduces Q gd and C gd by 32% and 22%, respectively, in comparison with C-TMOS.