Analyzing the Influence of SiO₂ Buried Layer Thickness and Positioning on the Performance of 20 nm N-MOSFETs

The continuous scaling of MOSFETs to meet the demands of high-performance devices has intensified challenges such as short-channel effects (SCEs), which degrade device reliability and efficiency. To address these issues, this study investigates the influence of SiO₂ buried layer thickness and vertical positioning on the electrical performance of 20 nm n-MOSFETs incorporating a high-k dielectric gate stack. Using TCAD Silvaco ATLAS, the research systematically evaluates how buried oxide thickness (10 nm to 50 nm) and depth (30 nm to direct contact with the channel) affect key device parameters, including threshold voltage (Vth), drain-induced barrier lowering (DIBL), breakdown voltage, ON current (Ion), leakage current (Ioff), and the Ion/Ioff ratio. Results show that increasing the buried layer thickness increases Ioff from 8.51 × 10⁻¹¹ A/m to 3.09 × 10-10 A/m at 50 nm, while Ion slightly increases to 2.3 × 10⁻³ A/m. Although this reduces the Ion/Ioff ratio from 2.37 × 10⁷ to 7.54 × 10⁶, it also significantly improves breakdown voltage from 85.09 V to 167.4 V at 10 nm thickness. Notably, the breakdown voltage decreases to 76.26 V at 50 nm. In terms of vertical positioning, placing a 10 nm SiO₂ buried layer in direct contact with the channel yields the highest breakdown voltage of 1186.7 V and the lowest Ioff of 5.15 × 10⁻¹¹ A/m, with an Ion/Ioff ratio of 3.62 × 10⁷. These results highlight that both the thickness and position of the buried oxide layer play a crucial role in suppressing SCEs and enhancing breakdown robustness.