Simulation Modeling and Investigation of Silicon on Insulator Devices

Abstract: This work provides a thorough comparative analysis between performance, reliability and scaling limits for the Silicon-on-Insulator (SOI) n-MOSFET architectures at the 5 nm technology node. Using high-fidelity TCAD simulations, the 5 nm Partially Depleted SOI (PDSOI) variant with an 8 nm silicon body and heavy channel doping (1 × 10^20 cm^−3) is contrasted against a threshold voltage tree-based optimization of a 5 nm Fully Depleted SOI (FDSOI) device incorporating 1.3 nm ultra-thin body (UTB) and lightly doped channel (1 × 10^10 cm^−3). The PDSOI variant is found to have an even better intrinsic f_T of 4.2 THz; however, it’s severely affected by floating-body instabilities, a severe kink-effect as well as very high lateral electric fields peaking at 20 MV/cm. On the contrary, the FDSOI topology can effectively suppress kink-effect and moderate electric field stress (6.6 MV/cm) for better electrostatic integrity. The key result here is the realization of body volume inversion for 1.3 nm FDSOI, which provides maximum electron mobility (473 cm^2/Vs); almost eightfold improvement compared to PDSOI along with a large drive current of 1050 µA. Moreover, the introduction of high-k dielectric such as Ta2O5 into this platform enables an unprecedentedly high I_ON/I_OFF ratio = 7.41 × 10^9 in FDSOI. It is argued that the 5 nm FDSOI platform offers the best combination of power efficiency, mobility and performance for future terahertz-scale integrated-circuits.