Optimized SOI Stacked Si Nanosheet Gate-All-Around FET With Ni(Pt)Si Silicide-First and Load-Si Thinning Techniques

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In this article, to optimize the performance of silicon-on-insulator (SOI) stacked Si nanosheet (NS) gate-all-around field-effect transistor (GAAFET) with long source/drain (S/D) regions, special process techniques of Ni(Pt)Si silicide-first and Load-Si thinning are successfully integrated in the experimental devices. Because of the introduced silicide-first process, the transistor performance merits of ON-current (I_on) and transconductance (Gm) are also increased by 34.19% and 80.55% for the reduction of 68.66% in the S/D parasitic resistance. Meanwhile, compared to the Bulk-Si GAAFET, the gate-induced drain leakage (GIDL) current of the SOI GAAFET is also decreased by more than one order of magnitude. However, the subthreshold characteristics of SOI GAAFETs exhibit a rapid degradation as the gate length (Lg) scaling, which is mainly due to the effect of parasitic channel in the remaining Load-Si layer. To optimize the leakage and subthreshold characteristics, the electrical impacts of Load-Si thickness (TLoad-Si) are thoroughly investigated by the experiment and TCAD simulation. The experimental SOI GAAFET fabricated by thinning Load-Si to 19 nm has obtained better subthreshold characteristics, improved normalizedI_on, and caused an obvious decrease of OFF-current (I_off) atLg=30nm. Meanwhile, the simulation results further show that the SOI GAAFET with shorterLgneeds to continuously decreaseTLoad-Sito meet the requirements of a fully depleted channel and lowI_off.