Analytical insights into threshold voltage behaviour of vertical linearly doped fully depleted silicon-on-insulator MOSFETs

This paper presents a novel two-dimensional (2-D) analytical model for the surface potential of a Vertical Linearly Doped (VLD) Fully Depleted Silicon-on-Insulator (FDSOI) MOSFET. Moreover, the channel electric field and threshold roll-off are modeled using the surface potential equations. The evanescent-mode analysis method has been utilized to obtain the channel potential, and ATLAS TCAD is used to simulate the subthreshold I-V characteristics of the device. The performance of the proposed device has been compared with the calibrated FDSOI MOSFET. The proposed device demonstrates remarkable improvements over conventional FDSOI MOSFETs: off-state leakage current plunges from 100 nA to 12 pA, while subthreshold swing sharpens from 110 mV/dec to 85 mV/dec, yielding an exceptional ON-to-OFF current ratio enhancement from 7.2 × 10 3 to 2.8 × 10 7 . The linearly doped channel in the proposed device is developed using the hetero epitaxy method. The proposed device can be used in integrated circuits (ICs) for low-power applications such as laptops and mobile phones.