TCAD simulation shows improved on-resistance and breakdown voltage in SiC MOSFETs, indicating design advantages.
In this work, TCAD simulation of SiC MOSFETs design with deep (2 µm) p-base using single step aluminum channeling implant along [0001] direction and JFET design using phosphorus implant is presented. The threshold voltage (V th ) was around 3 V for both the devices. Improvements to the specific on-resistance (R on,sp ) reduction by ~ 30 %, breakdown voltage (BV) enhancement by ~ 40 %, miller plateau (Q GD ) reduction by ~ 30% is reported. Furthermore, both the Baliga figure-of-merit (BFOM) (BV 2 /R on,sp ) and high-frequency figure-of-merit (HFOM) (R on,sp × Q GD ) with 2 µm deep p-base /JFET implant are enhanced as compared to shallow 0.7 µm p-base/JFET implant. This paper provides valuable insights into the advantages of a single-step channeling implant at room temperature, without the need for a hard mask. This approach offers a high throughput with a low-cost process for fabricating high-performance SiC MOSFETs.
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Vudumula et al. (2025) studied this question.
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