Optimizing 1.2 kV SiC Trench MOSFETs for Enhanced Performance and Manufacturing Efficiency

This paper presents the development and optimization of a 1.2 kV Silicon Carbide (SiC) Trench MOSFET with a Bottom P-well (BPW), designed to achieve a compact structure and a simplified fabrication process. By performing the BPW implant before the trench etching process and utilizing it in conjunction with a shallow trench, the process complexity was reduced while maintaining effective corner coverage of the trench gate. Comprehensive simulations and unit process analyses were conducted to evaluate the effects of the hard mask sidewall angle, P-well, and JFET implant doses on device characteristics. Optimal performance was achieved by introducing an additional P+ implant in the P-well region, which significantly enhanced breakdown voltage without affecting channel properties. The optimized device demonstrated a specific on-resistance (R on,sp ) of 2.2 mΩ·cm 2 , a breakdown voltage (BV) of 1600 V, and a threshold voltage (V th ) of 3 V, with potential further reductions in R on,sp through substrate thinning.