A 12-bit 20 MS/s SAR ADC for the readout of HFRS-TPC

This paper presents the design and implementation of a 12-bit, 20 MS/s successive approximation register (SAR) Analog-to-Digital Converter (ADC) chip, specifically tailored for the readout of the High-Energy FRagment Separator (HFRS) time projection chamber (TPC) detector. The proposed ADC architecture primarily comprises a capacitive Digital-to-Analog Converter (DAC), a comparator, a clock generation circuit, and asynchronous SAR logic. The internal DAC employs a hybrid switching strategy and integrates binary redundant capacitors to mitigate ADC conversion errors caused by incomplete settling of reference voltages and DACs. Additionally, dynamic comparators and dynamic digital logic are utilized to minimize power consumption. Fabricated in a 180 nm CMOS process, the chip features a core area of 800 μm× 550 μm and achieves a core power consumption of less than 3 mW at a supply voltage of 1.8 V.