Design of PFD and a charge pump for low power, low phase noise CP-PLL for sub-6 GHz applications

Abstract The work proposes a charge pump phase-locked loop (CP-PLL) featuring novel custom-designed Phase Frequency Detector (PFD) and Charge Pump (CP) circuits. A new perspective in NAND-gate-based PFD which achieves a dead-zone-free and blind-zone-free @ ±2 π rad operating range by incorporating delay elements in the reset path. The proposed CP integrates a switched capacitor and current-mode-logic–Quick current steering (CML-QCS) approach, along with a unity gain amplifier to eliminate phase error. The design attains a lock acquisition time of 3.8 μ s, and reference spur level of −74.811 dBc. The framework is validated with a current mismatch of 0.72 % over a 0.34–1.5V dynamic range, with CP current I CP of 97.5 μ A. The layout occupies an area of 14.49 X 14.58 μm 2 . The CP-PLLs figure of merit is computed as −182.79 dBc/Hz. The simulation findings at 2.56 GHz frequency with 3.54 mW of power, and −120.12 dBc/Hz of phase noise @ 1 MHz offset by using the Cadence UMC 180 nm process at a supply of 1.8 V. These outcomes indicate suitability for Bluetooth/WiFi applications with in Sub-6 GHz range.