A 10MHz-4.5GHz dead-zone free implicit reset path PFD and current mismatch-compensation charge-pump for low-spur PLLs in 180nm CMOS

The paper introduces a co-optimized phase-frequency detector (PFD) and charge pump (CP) front-end for wideband low-spur charge-pump phase-locked loops (CPPLLs). To eliminate the inherent dead-zone/blind-zone trade-off, an implicit-reset path PFD is proposed, where the reset operation is integrated into the core state-transition network, thereby eliminating the explicit reset buffer and its associated delay. This gives a dead-zone-free operation over a range of 10 MHz to 4.5 GHz of comparison frequencies. A nonlinear-amplifier-assisted CP is proposed to supplement the linear phase detection. It dynamically biases the current-steering switches in order to counteract channel-length modulation and switching nonlinearities, matching the charge/discharge currents of long and short pulses. The PFD-CP pair is simulated in a 180 nm CMOS process, and has a nominal 15 μA current with less than 0.5% mismatch over the entire tuning range, without trimming. Post-layout simulation results indicate a reference spur of -77.8dBc and 0.53ps RMS jitter at 4.5GHz, indicating its applicability to low-noise RF synthesizers and high-performance clock generation.