A Co‐Designed Implicit‐Reset Path PFD and Current Mismatch Compensated CP Enabling Sub‐0.5% Mismatch and Dead Zone‐Free for Low‐Spur PLLs

This paper presents a co‐optimized phase‐frequency detector (PFD) and charge pump (CP) front‐end for wideband, low‐spur charge pump phase‐locked loops (CPPLLs). To alleviate the fundamental dead zone/blind zone trade‐off, an implicit‐reset (output prediction logic‐based), PFD is proposed in which the reset function is embedded within the core state‐transition network, thereby removing the explicit reset buffer and its associated delay. This enables dead zone‐free operation over a comparison frequency range from 10 MHz to 4.7 GHz in postlayout simulation. To complement the linear phase detection, a nonlinear amplifier‐assisted CP is introduced. It dynamically biases the current‐steering switches to compensate for channel‐length modulation and switching nonlinearities, thereby equalizing the charge and discharge currents for both long and short pulses. Implemented in a 180‐nm CMOS process and validated through post‐layout simulations with extracted parasitics, the proposed PFD‐CP front‐end achieves a nominal 150‐μA pump current with less than 0.5% current mismatch across the full tuning range without trimming. System‐level simulation results in a PLL environment show a reference spur of −80 dBc and 0.50 ps of RMS jitter at 4.7 GHz, demonstrating the suitability of the proposed architecture for low‐noise frequency synthesis and high‐performance clock generation.