A 20-24-GHz DPSSPLL with Charge-Domain Bandwidth Optimization Scheme Achieving 61.3-fs RMS Jitter and -253-dB FoMJitter

High-performance phase-locked loops (PLLs) with sub-100-fs jitter are essential for advanced wireline and mmWave transceiver systems. Recent research emphasizes the exceptional phase noise (PN) in sampling PLLs, primarily due to their high phase detector gain [1], [2]. As shown in Fig. 1, to balance the PN contribution from reference input and VCO, conventional type-II subsampling PLLs (SSPLL) employ a current-domain gain/bandwidth control by adjusting the pulse width of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">φCP</tex> . However, the charging current and noisy stability resistor still impact the in-band PN significantly. Moreover, an off-chip loop filter capacitor is often required due to the large PD gain, leading to increased bill-of-materials costs. Passive type-I SSPLLs remove noise contributions from the charge pump and stability resistor Rz while allowing compact on-chip loop filter capacitors. Nevertheless, passive type-I SSPLLs typically rely on slope-controlled circuits for voltage-domain gain/bandwidth optimization, which compromises the reference PN and limits maximum achievable PD gain.