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Investigation of highly diffusive point defects during silicon plasma etching

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Numerical simulation models predict point defect behavior during silicon plasma etching, suggesting improved defect management in CMOS fabrication.

Cryogenic silicon etching at very low temperatures suppresses plasma-induced damage, enhancing device performance.
For silicon trench etching at 1200 eV, significant point defect distributions measured over a 100 μm region were observed.
Numerical models of defect diffusion were validated by photoluminescence measurements, linking etching conditions to point defect behavior.
Findings indicate that minimizing interstitial diffusion at low temperatures may be essential for high-performance CMOS applications.

Kuboi et al. (2025) studied this question.

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Numerical simulation models predict point defect behavior during silicon plasma etching, suggesting improved defect management in CMOS fabrication.