Scaling-Induced Noise Behavior in n-p-n SOI Double-Gate Tunnel FETs in Presence of Interface Traps

This article examines the noise behavior in n-p-n Silicon-on-Insulator (SOI) Double-Gate Tunnel Field Effect Transistors (DG TFETs) influenced by interface traps. The research integrates interface trap models, low and high-frequency noise mechanisms, and examines spectral density fluctuations caused by factors such as doping concentration, gate work function, scaling the device and gate engineered versions of the proposed architecture. Two frequencies, 1 MHz and 1 GHz, and two interface trap types (acceptor-like and donor-like) have been considered for the analyses. It is observed that any scaling related to the gate structure, particularly the length in the lateral as well as the vertical direction affects the noise response. The results conclude that in some cases, the carrier density is responsible for the trend in noise response, whereas in others, the current density. This article also proposes an analog figure of merit involving noise parameters, and a metric to represent actual noise-derived transconductance.