A SiC Power MOSFET Model With an Improved Description of the JFET Region

Based on the technology computer‐aided design (TCAD) simulation, a SPICE model of vertical silicon carbide power metal‐oxide‐semiconductor field effect transistor has been proposed with an improved description of the junction‐type field effect transistor (JFET) region. The model describes a tilted current channel through the gate voltage V G ‐controlled depletion layer and builds a direct correspondence between the resistance in the undepleted part and the current path in the JFET region. It is shown that in JFET region, the diffusion current takes about 18% of total current and has a large magnitude at high gate voltage. However, the diffusion current cannot be described by one‐dimension approximation. In addition, at high gate voltage (14 V) and high drain voltage, excess electrons diffuse to the JFET region and form a high density of accumulation electrons. In this case, a constant electron mobility is not good enough to describe the drain current. A two‐segment model of electric field and electron mobility through the one‐dimension drift approximation is adopted to improve the agreement between the SPICE model and the TCAD simulation by using slightly higher values of electron mobility and the injected electron density. A new SPICE model of C gs , C gd and C ds is also presented. The SPICE simulated two‐pulse transients show very good agreement with TCAD simulation.