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This is a Quantitative Study study.

October 12, 2025Physica Scripta

Explicit compact modeling of long channel junctionless square-gate FET

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The developed model shows excellent agreement with TCAD simulations, achieving less than 10% error across diverse conditions.
A unified drain current expression is derived using Pao-Sah's approach, improving the reliability of the modeling process.
The transformation to explicit form via Lambert W function enhances computational efficiency and simplifies calculations.
The derivation includes terminal charges which facilitate the extraction of intrinsic capacitances for advanced device applications.

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Implication

This model demonstrates improved accuracy for drain current and capacitance in junctionless transistors, indicating its potential for nanoscale devices.

Cite This Study

Affandi et al. (2025) studied this question.

synapsesocial.com/papers/68ebffcfdef9fcb308ff24bf https://doi.org/10.1088/1402-4896/ae11dd

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Implication

This model demonstrates improved accuracy for drain current and capacitance in junctionless transistors, indicating its potential for nanoscale devices.

Explicit compact modeling of long channel junctionless square-gate FET

Key Points

Discussion

Implication

Cite This Study

Explicit compact modeling of long channel junctionless square-gate FET

Key Points

Discussion

Implication

Cite This Study

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