This paper presents an analytical model for the I-V and C-V characteristics of cylindrical junctionless nanowire FETs. The obtained expressions are continuous and valid for all bias regimes, i.e., total depletion, partial depletion, and accumulation. Also, the formulation is entirely physics-based, with no fitting parameters, and very intuitive, since it describes the device as a gated resistor. Model validation is performed against TCAD results, demonstrating excellent agreement.
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Souza et al. (2024) studied this question.
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