Design and Implementation of AXI Interconnect based SerDes Architecture in NoC

High-speed data communication is essential in tackling the ever-increasing pressure on complex System-on-Chip (SoC) designs to process data quicker within Network-on-Chip (NoC) architectures. In this research work, we proposed the SerDes based AXI Interconnect architecture to be implemented for overcoming major bottlenecks of present NoC communication system which faces a scalability and high-speed data transmission problem. This work is filling the gap by taking a holistic approach to resolve deficiencies of legacy protocols by providing an improved, scalable and low power solution which makes it suitable for today’s real time processing applications. The approach includes advanced Serializer/Deserializer (SerDes) technology with AXI Interconnect, which are parallel-to-serial data converters that will help increase the overall data transfer rates. This architecture is unique as it integrates AXI protocol with an 8-to-1 serializer and 1-to-8 deserializer connected with a flexible routing. It is optimized for maximum data throughput with the lowest power. Further, data interoperates over NoC- for scalability and performance features a XY routing algorithm with virtual channel buffers and crossbar switch. Simulation and validation were carried out on Zynq UltraScale+ SoC platform, it shows that the proposed NoC architecture has advantages of data throughput enhancement, low latency and reduced power consumption over existing state-of-the-arts (HiFMP, Ring-based hybrid NoC and FFTM-2D NoC). The resulting architecture, with 1% resource utilization and a power consumption of 0.592 watts, performs better than other state-of-the-art designs with respect to both metrics..