High Performance and Low Power Axi-Lite 4 Master Controller Using System Verilog

Digital design and System-on-Chip (SoC) development practices frequently employ the Advanced eXtensible Interface (AXI) protocol. It acts as an interconnect protocol to help different semiconductor chip components communicate with one another. The AXI protocol, created by ARM, provides master and slave devices with a reliable and effective way to send data, control, and configure settings in a coherent and coordinated way. AXI provides high frequency and high performance designs. It is an on-chip communication protocol, Large bandwidth and frequency low-delay designs are suitable for it.The paper demonstrates the development of a high-performance and low power design utilizing the AXI Lite protocol. This design incorporates a state machine and is synthesized in Xilinx Vivado and resulting in an IP master module capable of functioning with both AXI4 and AXI4 slave interfaces.