Designing Energy-Efficient Hardware Accelerators for Computer Vision Applications

Computer vision has doubled its pace in recent years with various applications such as auto-driving cars, real-time surveillance, etc., creating the need for efficient hardware accelerators that can perform tasks with high speed and minimum energy consumption. Dedicated processors like CPU and GPU and their multiplications have computational power; however, they cannot meet the limited power budget relevant to edge and embedded systems. High-performance reconfigurable computing has become one of the main solutions to this problem, where hardware accelerators like FPGAs, ASICs and special-purpose architectures have shown great promise. This paper aims to give detailed information, performance enhancement approaches, and the best practices in developing energy-efficient accelerators suitable for computer vision tasks. Here, we discuss the choices of architectural paradigms, data format flow directionality, memory management hierarchy, and power management. The paper also covers various trade-offs in performance, power consumption and hardware cost, with examples and benchmarks on best practices. Through the use of novel computing approaches like approximate computing and neuromorphic computing, as well as the integration of complementary architectures, this research will be instrumental in creating low-power computer vision systems in the future.