Analog and Temporary On-chip Memory for ANN Training and Inference

On-chip training at the edge becomes a primary requisite for real-time and security-sensitive artificial neural network (ANN) applications. In-memory computation (IMC) techniques have been proposed to facilitate data-intensive computational operations in ANNs. IMC with bidirectional multiply-accumulate (MAC) accelerates ANN on-chip training but suffers from significant communication overhead between the MAC engine and the off-chip storage containing the intermediate data. This paper proposes an analog temporary on-chip memory (ATOM) to store this intermediate data. The ANN training architecture with the proposed ATOM has two significant advantages. First, the energy required to store intermediate data is scaled down by ∼20× due to the analog and temporary nature of the memory. Second, the proposed architecture avoids power and area-consuming analog-to-digital converters (ADCs) between neural network stages. The ATOM cell measurements are carried out from 20 fabricated dice, and the impact of ATOM characteristics on ANN system training and inference performance is analyzed. This paper shows significant latency improvement of ∼10× and area savings of ∼5× for intermediate data storage compared to the on-chip SRAM during ANN training's forward and backward pass operations. An improvement in the area and latency will be beneficial to instrument the area-and energy-efficient hardware system for on-chip ANN training.