Design of infrared FPA digital ROIC architecture with frame integration

Signal-to-noise ratio (SNR) and dynamic range (DR) are important indicators to measure the performance of infrared focal plane array readout integrated circuit (IRFPA ROIC). Applying frame integration technology to readout integrated circuit can effectively improve its SNR and DR, and improve the sensitivity and detecting capability of infrared imaging system. This paper studies the realization of frame integration technology in a readout integrated circuit, and proposes a column-level digital readout integrated circuit structure with frame integration function. The column-level analog-to-digital conversion part of the architecture adopts single-slope analog-to-digital conversion circuit (SS-ADC) with number setting function, and a low-power static random access memory (SRAM) is integrated on the chip.After integration and amplification, the signal is stored in the SRAM array which is corresponding with the pixel array, then accumulated frame by frame through a settable SS-ADC, which realizes the efficient accumulation and storage of multi-frame digital signals. The circuit simulation analysis of the frame integration function of the architecture is completed. The results show that the architecture design can effectively accumulate digital signals from multiple frames, equivalently enhance the charge processing capability of the readout integrated circuit, and prolong the integration time,which can realize a frame integration column-level digital readout integrated circuit that is suitable for small pixel size, high integration and simple design. This design improves the on-chip information processing ability of column-level digital readout integrated circuit, and has certain application value under the development requirements of large dynamic range, high sensitivity and low noise of readout integrated circuit.