A Reconfigurable and Adaptive Macro-pixel Based SPAD Array Readout Circuit

To address the susceptibility of single-photon avalanche diodes (SPADs) to false triggering under strong background illumination and the lack of flexibility in traditional macro-pixel readout architectures, this paper proposes an FPGA-based adaptive and reconfigurable macro-pixel SPAD array readout circuit. The design employs a modular, tileable architecture that enables flexible array scaling, complemented by a reconfigurable coincidence-detection threshold together with a feedback regulation mechanism. These features enable automatic optimization of the detection strategy according to the incident optical power, thus supporting both high-sensitivity and high-signal-to-noise ratio (SNR) operating modes. The circuit incorporates a 216-stage delay-line time-to-digital converter (TDC), achieving a time resolution of 25.11ps, with a typical power consumption of 1.2 W. Measurement results show that the differential nonlinearity (DNL) ranges from –0.89 to 0.77 LSB, and the integral nonlinearity (INL) ranges from –1.80 to 1.53 LSB. Based on Monte Carlo simulations and FPGA-level validation, the proposed readout architecture maintains stable macro-pixel signal-to-noise ratio and detection efficiency under varying background illumination. This work presents a scalable hardware architecture that enables adaptive readout for large-scale SPAD arrays, suitable for laser ranging and imaging under varying background conditions.