Implementation of 32-bit Multiplication Unit for a Out-of-Order RISC-V Processor utilizing Radix-4 Booth Algorithm and Wallace Tree

Multiplication is a fundamental arithmetic operation critical to a broad spectrum of computational applications. Its implementation in hardware significantly influences overall system performance, given that multiplication inherently involves a series of successive addition operations, which can introduce potential bottlenecks in pipelined systems. This paper focuses on the design and implementation of an efficient 32-bit multiplier unit for educational purposes, within the context of a superscalar out-of-order RISC-V architecture, by utilizing and presenting standard techniques used on the industry in order to achieve fast multiplication results.