What question did this study set out to answer?

To develop a high-performance, low-overhead RV32IM RISC-V CPU core optimized for cryptographic workloads like SM3 and SM4 through arithmetic microarchitectural enhancements without specialized instructions.

August 16, 2026Advanced ElectromagneticsOpen Access

Design and Implementation of a High-Performance RISC-V CPU IP Core for Multiple Cryptographic Algorithms

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Authors

YCY. J. ChengXi’an University of Posts and Telecommunications YCYin C.-R.Xi’an University of Posts and Telecommunications KTK.X. TangCentral South University

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Implication

Experimental hardware evaluation demonstrates reduced arithmetic latency in an RV32IM RISC-V CPU core, highlighting efficient cryptographic processing for secure embedded systems.

Key Points

To develop a high-performance, low-overhead RV32IM RISC-V CPU core optimized for cryptographic workloads like SM3 and SM4 through arithmetic microarchitectural enhancements without specialized instructions.
Designed a hierarchical multiplier (with 4–2 compressor-tree reduction and look-ahead adder) and an enhanced radix-4 SRT divider (with leading-zero detection, result caching, and dynamic iteration control).
Implemented all modules in Verilog across a five-stage RISC-V pipeline, followed by functional verification via an RVM test suite and FPGA-based evaluation.
The optimized multiplier produced 64-bit outputs in a single clock cycle under 32-bit operations.
Multiplication latency was reduced by more than 70% relative to conventional Wallace-tree implementations.

Cite This Study

Cheng et al. (2026) studied this question.

synapsesocial.com/papers/6a8179eff2fb91fc834ad6e7 https://doi.org/10.7716/aem.v15i3.3355

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Implication

Experimental hardware evaluation demonstrates reduced arithmetic latency in an RV32IM RISC-V CPU core, highlighting efficient cryptographic processing for secure embedded systems.

Design and Implementation of a High-Performance RISC-V CPU IP Core for Multiple Cryptographic Algorithms

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Implication

Key Points

Cite This Study

Design and Implementation of a High-Performance RISC-V CPU IP Core for Multiple Cryptographic Algorithms

Discussion

Member takes

Implication

Key Points

Cite This Study

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