A 10-bit 70-MS/s SAR ADC with Reference Buffer in 40nm CMOS

A 10-bit 70-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with reference buffer is presented in this paper. Segmented capacitive DAC with redundant 2bits is designed to relax the design of reference buffer. A hybrid switching sequence is applied to the ADC to optimize power consumption. The Measurement results Show that the core SAR ADC achieves 48.52 dB SNDR and 56.67 dB SFDR at 70 MS/s sampling rate and Nyquist input frequency, consuming 2.50mW power consumption, achieving a FoM of 163.6 fJ/step. The ADC occupies an active area of 0.017 mm2 in 40nm CMOS technology.