Effective control of device geometry is key to mitigating high localized electric fields in next-generation SiC power devices. Advanced trench processing allows for highly tunable trench-gate architectures in trench MOSFETs. By utilizing a two-step inductively coupled plasma reactive ion etch (ICP-RIE) process, a high degree of trench base corner rounding can be achieved, irrespective of trench opening corner geometry prior to post etch treatments. Sentaurus TCAD device modelling highlights the importance of effective electric field dispersion at the gate oxide using rounded trench corners, while I-V characterization of fabricated trench MOS-capacitor devices demonstrate the influence of trench base corner rounding on gate oxide breakdown.
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Jones et al. (2024) studied this question.
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