Pushing the Time Resolution of the FPGA-Based Vernier Time-to-Digital Converter below the Circuit Transition Time

In this study, a Vernier time-to-digital converter (TDC) was investigated with a time resolution less than the signal transition in the circuit. A Xilinx FPGA was employed to implement the TDC. In this design, the timing difference between the two paths were generated by interconnects rather than LUT devices. Since the nature of uncertainty, a statistical model was proposed to analyze the output. Three methods were proposed to determine the output thermometer code. The time resolution can be around 5 ps in our measurement. As the resolution can be determined below the signal transition, it is promising to push the resolution down into sub-ps for FPGA-based TDCs by suitable interconnections.