Performance evaluation of Near-Threshold Ultradeep Submicron Digital CMOS Circuits using Approximate Mathematical Drain Current Model

This paper examines CMOS inverter performance near threshold voltage using a tailored drain current model for submicron nodes up to 22nm. Validated via HSPICE simulations, the model incorporates factors like inverse narrow width effect, Miller capacitance, and layout dependencies. Demonstrating continuity and precision across a wide operational spectrum, results indicate deviations within 1-5%, affirming the model’s robustness.These findings underscore its utility for designers grappling with the intricacies of near-threshold voltage operation, offering a reliable framework to optimize CMOS inverter performance in ultra-deep submicron technologies.