A Case Study on Formal Sequential Equivalence Checking based Hierarchical Flow Setup towards Faster Convergence of Complex SOC Designs

Functional Verification Sign-Off is the crux of the design verification problem faced by latest Silicon Designs on the Simulation/Stimulus Driven and the Formal Verification Platforms.Formal Verification Convergence is a custom specific criterion depending on the success, failure, exhaustiveness and reachability of the verification goals generated and validated by the Formal Tool.One of the key techniques in Formal Verification is the ability to mathematically prove the equivalence between two different versions of the same RTL Designs.Those RTL Design versions may differ in terms of Feature addition/removal or Bug Fixes or Low Power Capability or specific requirements.Synopsys VC Formal TM tool provides this formal verification technique using a built-in Formal Application known as 'Sequential Equivalence (SEQ)' App.This Case Study outlines various approaches in deploying Formal SEQ App and an approach towards Faster Convergence.