Optimal Test Scenarios based Regression Suite for Functional Verification Closure of Advanced Digital Designs

Computational and Performance Intensive applications like Graphic Processing, Virtual Gaming, Augmented Reality, AI Inferencing and Machine Learning have led to higher order of complexity in the Semiconductor Chips. Functional Verification stage continues to play an impactful role in the quality and schedule of ASIC/SOC development cycle. Coverage Driven Functional Verification Closure with highest possible Coverage metric and most efficient verification schedule that can be achieved by Constrained Random Verification Test Scenario based Verification or by Mathematical Model based Proofing Formal Verification is a challenging task. In this work, a configuration is proposed for an advanced digital design with multiple inter-dependent finite state machines (FSMs) & combinatorial logic by utilizing the percolation of the Test and Input Stimulant Space in the Design Under Test (DUT) to establish an optimal group of test scenarios.