A Study of the Reusability of UVM-Based SPI Verification IP

This paper proposes an integrated UVM (Universal Verification Methodology)-based verification environment with scalability and reusability through Verilog-HDL (Hardware Description Language) design and UVM-based VIP (Verification IP) development for SPI (Serial Peripheral Interface) which is representative protocols of low-speed serial communication. The proposed verification environment enables reusable stimulus generation and random test using UVM, a class library implemented by System Verilog, and shows classes with various scalability with Built-in Base Class. In addition, Scoreboard and Functional Coverage were performed to show the reliability and efficiency of verification of each VIP