Design and performance analysis of 4H-SiC LDMOS

Integration and miniaturization are the development directions of power electronics in the future. In this paper, SiC-LDMOS is successfully fabricated on a p-type epitaxial layer for high-power integrated circuits. By extracting the transfer characteristics, output characteristics and breakdown characteristics of SiC-LDMOS, the impact of varying drift region parameters and channel length on device performance is investigated. The experimental results show that when the drift region length is 10 μm, the doping concentration is 7×10 16 cm -3 and the channel length is 1 μm, SiC-LDMOS exhibits the best comprehensive performance with a breakdown voltage of 1130 V, a specific on-resistance of 14.6 mΩ·cm 2 and a figure of merit of 87.4 MW/cm 2 . Compared with previously reported SiC lateral MOSFETs and SiC-LDMOS, our device exhibits superior performance.