What question did this study set out to answer?

Fabricate and evaluate a 4H-SiC lateral double-implanted MOSFET on an insulating substrate to improve device blocking voltage.

April 1, 1998IEEE Electron Device Letters

6 kV 4H-SiC lateral DMOSFETs

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Authors

JSJ. SpitzPurdue University West Lafayette MMM. R. MellochPurdue University West Lafayette JCJames A. CooperPurdue University West Lafayette

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Implication

Experimental study demonstrates a 2.6 kV blocking voltage in 4H-SiC lateral DMOSFETs, indicating significant power-handling improvements over vertical designs.

Key Points

Fabricate and evaluate a 4H-SiC lateral double-implanted MOSFET on an insulating substrate to improve device blocking voltage.
Fabricated an LDMOS field effect transistor in a lightly doped n-type epilayer grown on an insulating 4H-SiC substrate.
Tracked depletion region extension laterally toward the drain and compared voltage limits against vertical DMOSFETs on conducting substrates.
Achieved a blocking voltage of 2.6 kV in the lateral 4H-SiC DMOSFET.
Nearly doubled the maximum blocking voltage previously demonstrated for any silicon carbide MOSFET.

Cite This Study

Spitz et al. (1998) studied this question.

synapsesocial.com/papers/6a91053eaa0a5bd9a2e1b287 https://doi.org/10.1109/55.663527

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Implication

Experimental study demonstrates a 2.6 kV blocking voltage in 4H-SiC lateral DMOSFETs, indicating significant power-handling improvements over vertical designs.

6 kV 4H-SiC lateral DMOSFETs

Discussion

Member takes

Implication

Key Points

Cite This Study

6 kV 4H-SiC lateral DMOSFETs

Discussion

Member takes

Implication

Key Points

Cite This Study

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