The Illusive Failure-Atomic Double-Width Compare-And-Swap

This paper explores the limitations of failure atomicity in Intel's Double-width Compare-and-Swap (DWCAS), an essential instruction for lock-free and wait-free algorithms in concurrent computing. DWCAS, known as cmpxchg16b on the Intel platform, can manipulate a pair of consecutive (and properly aligned) 8-byte words in a manner that makes updates to these memory locations visible atomically, at least in traditional systems with volatile main memories. At the same time, Intel's technical documents warn that only 8-byte stores are guaranteed to be power-fail atomic in systems equipped with non-volatile memories, meaning that such operations cannot be torn by a power failure. We review the implications of this limitation on the integrity of algorithms that assume DWCAS is both atomic in the traditional sense and also failure-atomic. Through this analysis, we aim to clarify misconceptions and advocate for robust software-based alternatives to ensure true power-fail atomicity in DWCAS operations.