CFPara: a combination of coarse and fine-grained FPGA parallel routing methods

FPGA is an emerging hardware productivity that is characterized by high flexibility, reconfigurability and moderate cost. The development of FPGA EDA software is relatively lagging behind due to the problems of difficult programming and excessive compilation time, which constrains the upward expansion of the FPGA field. In this paper, we aim to solve the problem of long compilation time of FPGA EDA software, and make an in-depth study on routing, which is one of the most time-consuming steps in the compilation process. A combination of coarse- and fine-grained FPGA parallel routing algorithm is proposed. Coarse-grained routing uses a load-balanced space partitioning strategy to generate a routing sequence tree, and when routing each net mesh, it switches to a fine-grained parallel algorithm to perform parallel routing within the net mesh with one source-sink node pair. Experiments show that the CFPara algorithm proposed in this paper compared to the VPR PathFinder algorithm can obtain a 11.7× speedup ratio.