From Topology to Realization in FPGA/VPR Routing

Versatile Place and Route (VPR) enabled the exploration of diverse FPGA architectures. OpenFPGA extended VPR through bitstream generation and added silicon compilation. Our work is one of several efforts to use this combination to build commercial devices, which, to achieve competitiveness, has necessitated several improvements to routing and elsewhere for area, power, and performance. Fitting to the MCNC and VTR benchmarks using this work, our first improved routing pattern yields a 22% reduction in metal loading, a 14% reduction in routing multiplexer input pin count per function tile, and a 10% reduction in source to farthest sink paths. For this, routed length increased 5%, the proportion of net detours increased 11%, router heap operations increased 16%, and router iterations increased 42%, as the unmodified VPR router worked harder on routing with fewer switches but without introducing any routing failures. This work provides the first steps to a routing compiler for OpenFPGA/VPR, much as ASIC/SoC flows use a memory compiler.