A Power-Efficient Autonomous Current Adaptation ADC Input Driver

This paper presents a power-efficient autonomous current adaptation input driver (ACAID) for analog-to-digital converters (ADCs), which employs floating-gate transistors to provide reconfigurability. The proposed ACAID autonomously increases the supply current at the onset of the tracking phase, achieving a high slew rate. As the driver output voltage gradually follows the input signal in the RC-settling or hold phase, the supply current successively diminishes back to the original low quiescent level. The required sensing and actuating circuits for current adaptation are inherent components in the adopted capacitive feedback topology. A prototype version of the proposed ACAID has been designed and fabricated in a <tex-math notation="LaTeX">0.35</tex-math> CMOS process, along with integrated charge programming circuits and a 10-bit successive approximation register ADC. With <tex-math notation="LaTeX">0.5</tex-math> sampling capacitors loading the driver, the proposed ACAID achieves <tex-math notation="LaTeX">-70.1</tex-math> total harmonic distortion (THD) with a <tex-math notation="LaTeX">100</tex-math> input signal with <tex-math notation="LaTeX">2.8</tex-math> amplitude. When connected to an on-chip ADC with a <tex-math notation="LaTeX">200</tex-math> sampling rate, the measured effective number of bits (ENoB) near the Nyquist rate is 9.1. The proposed ACAID saves more power as the input frequency increases or when the portion of the tracking period reduces. The prototyped driver circuit can save <tex-math notation="LaTeX">$49.5%$</tex-math> power consumption when the input frequency is <tex-math notation="LaTeX">100</tex-math> with a <tex-math notation="LaTeX">$10%$</tex-math> duty cycle for tracking. The power-saving ratio can be up to <tex-math notation="LaTeX">$76.2%$</tex-math> when the sampling rate increases to <tex-math notation="LaTeX">1</tex-math> .