This paper presents a 14-bit, 2-kS/s continuous-time incremental delta-sigma ADC (CT-IADC) for low-frequency, multiplexed sensor interfaces, including geomagnetic-field and temperature monitoring. The proposed CT-IADC targets high-resolution conversion of slowly varying signals without a dedicated front-end anti-aliasing filter or a high-drive sensor buffer. A first-order continuous-time loop filter is combined with reset-based incremental operation and a second-order cascade-of-integrators (COI) digital filter. To improve area and linearity in the multi-bit feedback path, a pulse-number-modulated (PNM) feedback DAC generates multi-level feedback by varying the number of uniform, fixed-width pulses, converting pulse-edge non-idealities into an approximately code-independent gain error. A 3-bit reference-less flash quantizer based on complementary self-biased differential amplifiers (CSDAs) realizes quantization thresholds through transistor aspect-ratio scaling, eliminating the resistive reference ladder and reducing signal-dependent kickback at the integrator input. Fabricated in a 180-nm CMOS process, the prototype operates with a 2.048-MHz sampling clock, an OSR of 1024, and a 1-kHz signal bandwidth. The ADC core occupies 240 μm × 526 μm and consumes 379 μW from a 1.8-V supply. Measured with a 125.69-Hz differential sinusoidal input, the CT-IADC achieves an SNDR of 80.2 dB, corresponding to a 13.02-bit ENOB, at a 2-kS/s output rate in incremental mode. For loop characterization, the same continuous-time loop is also operated in continuous-time delta-sigma modulator mode, achieving an SNDR of 83.9 dB and a dynamic range of 90.04 dB.
Lee et al. (Mon,) studied this question.