A 188.6-μW Continuous-time Incremental Delta-Sigma ADC with Extended Counting achieving 95.2-dB SNDR and 175.4-dB FoMSNDR

Delta-sigma <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(ΔΣ)</tex> analog-to-digital converters (ADCs) are well-known for oversampling and noise-shaping techniques to achieve high resolution and good power efficiency. However, free-running <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ΔΣ</tex> ADCs are dynamic systems with memory that cannot offer one-to-one mapping between input and output samples. Therefore, incremental delta-sigma <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">( ΔΣ)</tex> ADCs, resetting their modulators and decimation filters after each conversion, were invented for multiplexed applications. Up until now, most <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ΔΣ</tex> ADCs are implanted in discrete-time style. While they can realize high resolution at a relatively low cost, their switched-capacitor circuits put high requirements on the input drivers, which can consume much more power than the ADC itself. Continuous-time <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ΔΣ</tex> ADCs, with the resistive input impedance, can significantly simplify the design of the input driver, making them well-suited for higher-speed sensing applications.